1. Field of the Invention
The present invention relates to clock line drivers for integrated circuits. In particular, the invention relates to parallel arrangements of drivers to drive high capacitance clock lines.
2. Description of Related Art
The capacitance associated with a CCD clock line may be too large to be driven by a single off-chip clock driver. Consequently, multiple off-chip clock-drivers are required to be connected (off-chip or on-chip) to the single CCD clock line. The connection of multiple clock-drivers to a single CCD clock line creates performance and reliability issues. One clock driver momentarily in a high state may source current from its output into the output of an adjacent clock driver, whose outputs are tied together, and where the second clock driver's output is momentarily in a low-state. This causes a driver cross-over current rather than charging the intended CCD clock line. The driver cross-over current occurs when there is a low-impedance path between a high output of one clock driver and a low output of another clock driver that has been tied together. Such an occurrence starves the clock line from early current needed to provide fast rise/fall time and can lead to electrical damage of the clock drivers.
In a known TDI sensor, the CCD electrodes of a single clock phase of the TDI imaging region were grouped into two halves. In a first half, electrodes comprising a first portion of the particular phase were electrically connected together by a metal bus with two bond pads connected to the metal bus. Similarly, in a second half, electrodes comprising a second portion of the particular clock phase were connected together by their own metal bus with two bond pads connected to the metal bus. The two bond pads of the first half and their connected bus were electrically independent from the two bond pads of the second half and their connected bus. In this TDI sensor, the electrodes of the first half were clocked by one pair of clock drivers and the electrodes of the second half were clocked by another pair of clock drivers. In this approach, the capacitances of the first and second halves were reduced relative to the capacitance of the entire imaging area. However, in this arrangement, driver cross-over currents could still occur if differences in propagation delay through the clock drivers of a clock driver pair result in a time skew in the driver clock signals since there was a low-impedance path between a high output of one clock driver and a low output of another clock driver that had been tied together in either the first or second half of the imaging areas. This arrangement was duplicated for each clock phase.
U.S. Pat. No. 6,108,032 to Hoagland describes a plurality of photo-sensitive cells arranged in rows and columns. These pixel rows are further arranged into a number of row segments, where each row segment corresponds to a separate clocking section. Each row segment is clocked in parallel; however, the row segments are clocked at different clocking frequencies to compensate for image motion of objects contained in the scene. Hoagland varies the clocking rates applied to the different row segments to compensate for relative motion differences within the image. However, in column 15, lines 4–7, Hoagland describes that a camera control unit 406 can command that the clocking of all row segments be done at the same rate (uniform IMC) when objects contained in the scene will have the same relative forward motion. Nevertheless, Hoagland does not connect together the inputs of clock drivers as is done in the present invention. Unlike the present invention, Hoagland is not concerned with and does not address the present problem of providing enough current to drive a CCD with a high RC constant at high speeds, and does not disclose a plurality of external clock drivers.
U.S. Pat. No. 5,155,597 to Lareau, et al., describes an imaging array with motion compensation where charge transfer rates of several column groups are varied according to a rate of motion to affect motion compensation.